VLSI (Very Large Scale Integrated) devices include microprocessors and custom circuit devices. Custom circuit devices include ASICs (Application Specific Integrated Circuits) and programmable devices. Generally, the ASICs are designed and manufactured to perform a specific implementation. The programmable devices include non-reconfigurable devices and reconfigurable devices. The non-reconfigurable devices use fuse or antifuse technology to form permanent interconnects between various logical components and circuits. The reconfigurable devices use reconfigurable interconnects implemented with programmable switches to route signals between logical components and circuits. The reconfigurable devices include PLDs (Programmable Logic Devices), FPGAs (Field Programmable Gate Arrays), and reconfigurable DSP (Digital Signal Processing) devices.
An FPGA is illustrative of the reconfigurable devices in general. The FPGA includes logic cells coupled by interconnect wires which include reconfigurable switches. The interconnect wires and the reconfigurable switches allow data to be transferred between any two of the logic cells.
In current VLSI technology, data communication has a significant impact on a device's cost and performance. The data communication uses hardware resources, such as interconnect wires, which affects the cost of the device. Delays in the data communication affect the performance of the device. As VLSI technology continues to scale features downward and to increase device density, the impact on the cost and the performance of the device will increase. For example, greater numbers of transistors will result in greater numbers of the interconnect wires increasing the cost. Smaller transistors will result in greater packing densities of the transistors, which will require reducing cross sectional size of the interconnect wires increasing transmission delays as signals traverse the interconnect wires. Faster transistors will lead to faster clock cycle speeds, which will increase the impact of the delays associated with the data communication.
The impact of the data communication on the cost and performance is particularly significant for the reconfigurable devices such as the FPGAs. In a custom circuit device implemented with an FPGA, the time for signals to traverse the interconnect wires and the reconfigurable switches often takes up a large fraction of a clock cycle period. Furthermore, running out of interconnect resources is a common problem that often constrains the usable fraction of logic resources of a reconfigurable device. For the reconfigurable devices, it would be advantageous to be able to more efficiently use the interconnect resources.
Traditional design flow of a custom circuit device such as an ASIC or a reconfigurable device is phased, with abstractions between the phases. A common design approach is to specify a register transfer level (RTL) design in a high-level description language such as Verilog or VHDL. The RTL design is then fed through a hardware synthesis tool followed by a place and route tool. Such a design flow is common for both the ASICs and the FPGAs. The RTL design specifies the operation of hardware at a clock cycle level, i.e., what should happen at each clock cycle. Subsequent steps in the design flow have very little flexibility in altering what happens in each cycle or for inserting additional clock cycles. Any such adjustments, if at all possible, are very local and have to be done under very stringent restrictions, such as preserving the relative latency (in number of clock cycles) of different paths that diverge and subsequently merge.
By the time the traditional design flow reaches place and route, the level of abstraction has gotten very low. At this point, data transport requirements are represented at the level of unshared wires. The unshared wires are routed by the place and route tool. Decisions regarding data transfers and scheduling of operations for the device are frozen in the RTL design. In the traditional design flow, it is not possible to leverage accurate placement information when making these decisions. Further, since the scheduling of the operations in the device is fixed in the RTL design, it is not possible to accommodate changes to interconnect latency in subsequent phases of the design flow.
What is needed is a design procedure which allows more efficient use of interconnect resources.